To achieve faster operating speeds, integrated circuits (ICs) are being developed with smaller feature sizes and higher densities of components. Conductivity of metal interconnections has emerged as a limitation in the development of these high performance devices. Forming electrically conducting vias, contacts, and conductors of copper or other metals becomes increasingly challenging as feature sizes are reduced. Techniques for forming such metal features include physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) and electrochemical deposition (also referred to as electroplating or electrodeposition.)
The conventional electroplating process includes steps as described in the following. The wafer is first immersed in an electrolytic bath containing metallic ions and is biased as the cathode in an electric circuit. With the solution positively biased, the metallic ions become current carriers which flow towards and are deposited on the exposed surfaces of the wafer. As the designed feature sizes become smaller and smaller, there are several obstacles which need to be overcome for the formation of small embedded damascene metal features.